The following tutorial, by Stuart Sutherland of Sutherland HDL, is an updated version of a paper presented at HDLCon in March 2000. It provides an overview of the changes in the Verilog-2001 standard.

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation.… ...